์ „์ž๋ถ€ํ’ˆ ๋ฐ์ดํ„ฐ์‹œํŠธ ๊ฒ€์ƒ‰์—”์ง„
  Korean  โ–ผ

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

P3C1011 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Pyramid Semiconductor Corporation

๋ถ€ํ’ˆ๋ช… P3C1011
์ƒ์„ธ๋‚ด์šฉ  HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM
Download  10 Pages
Scroll/Zoom Zoom In 100% Zoom Out
์ œ์กฐ์‚ฌ  PYRAMID [Pyramid Semiconductor Corporation]
ํ™ˆํŽ˜์ด์ง€  http://www.pyramidsemiconductor.com
Logo 

P3C1011 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Pyramid Semiconductor Corporation

 
Zoom Inzoom in Zoom Outzoom out
/ 10 page
 1 / 10 page
background image
1
Document # SRAM131 REV OR
Revised March 2006
P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
High Speed (Equal Access and Cycle Times)
โ€” 10/12/15/20 ns (Commercial)
โ€” 12/15/20 ns (Industrial)
โ€” 20/25/35 (Military)
Low Power
โ€” 360 mW (max.)
Single 3.3V ยฑ 0.3V Power Supply
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
FEATURES
DESCRIPTION
The P3C1011 is a 131,072 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ยฑ 0.3V tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1011
is a member of a family of PACE RAMโ„ข products offer-
ing fast access times.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0 to A17. Reading is
accomplished by device selection (
CE and output en-
abling (
OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE or OE is HIGH or WE is
LOW.
For both reading and writing, the Byte Enable control lines
(
BLE for I/O
0-7 and BHE for I/O8-15) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
Package options for the P3C1011 include 44-pin SOJ and
TSOP packages.
2.0V Data Retention
Easy Memory Expansion Using
CE
CE
CE
CE
CE and OE
OE
OE
OE
OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down when deselected
Packages
โ€”44-Pin SOJ, TSOP II
SOJ
TSOPII


Html Pages

1  2  3  4  5  6  7  8  9  10 


๋ฐ์ดํ„ฐ์‹œํŠธ Download




๋งํฌ URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET ๊ฐ€ ๊ท€ํ•˜์— ๋„์›€์ด ๋˜์…จ๋‚˜์š”?  [ DONATE ]  

Alldatasheet๋Š”?   |   ๊ด‘๊ณ ๋ฌธ์˜    |   ์šด์˜์ž์—๊ฒŒ ์—ฐ๋ฝํ•˜๊ธฐ   |   ๊ฐœ์ธ์ •๋ณด์ทจ๊ธ‰๋ฐฉ์นจ   |   ์ฆ๊ฒจ์ฐพ๊ธฐ   |   ๋งํฌ๊ตํ™˜   |   ์ œ์กฐ์‚ฌ๋ณ„ ๊ฒ€์ƒ‰
All Rights Reservedยฉ Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn