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CS5330A-BS 데이터시트(PDF) 7 Page - Cirrus Logic |
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CS5330A-BS 데이터시트(HTML) 7 Page - Cirrus Logic |
7 / 16 page DS138F5 7 CS5330A/31A SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VA+; CL = 20 pF) Switching characteristics are guaranteed by characterization. 9. 10. 11. Parameter Symbol Min Typ Max Unit Output Sample Rate Fs 2 - 50 kHz MCLK Period MCLK/LRCK = 256 tclkw 78 - 1000 ns MCLK Low MCLK/LRCK = 256 tclkl 31 - 1000 ns MCLK High MCLK/LRCK = 256 tclkh 31 - 1000 ns MCLK Period MCLK/LRCK = 384 tclkw 52 - 1000 ns MCLK Low MCLK/LRCK = 384 tclkl 20 - 1000 ns MCLK High MCLK/LRCK = 384 tclkh 20 - 1000 ns MCLK Period MCLK/LRCK = 512 tclkw 39 - 1000 ns MCLK Low MCLK/LRCK = 512 tclkl 13 - 1000 ns MCLK High MCLK/LRCK = 512 tclkh 13 - 1000 ns MASTER MODE SCLK falling to LRCK tmslr -10 - 10 ns SCLK falling to SDATA valid tsdo -10 - 35 ns SCLK Duty cycle -50 - % SLAVE MODE LRCK duty cycle 25 50 75 % SCLK Period tclkw (Note 9) -- ns SCLK Pulse Width Low tclkl (Note 10) -- ns SCLK Pulse Width High tclkh 20 - - ns SCLK falling to SDATA valid tdss - - (Note 11) ns LRCK edge to MSB valid tlrdss - - (Note 11) ns SCLK rising to LRCK edge delay tslr1 20 - - ns LRCK edge to rising SCLK setup time tslr2 (Note 11) -- ns 1 64 Fs 1 128 Fs - 15 ns 1 256 Fs + 5 ns |
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