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CS42528 데이터시트(PDF) 4 Page - Cirrus Logic |
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CS42528 데이터시트(HTML) 4 Page - Cirrus Logic |
4 / 91 page 4 DS586F1 CS42528 10.1.4 Circuit Board Layout ............................................................................................................ 80 11. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 81 11.1 AES3 Receiver External Components .......................................................................................... 81 12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 82 13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 84 14. PACKAGE DIMENSIONS ............................................................................................................... 88 THERMAL CHARACTERISTICS .......................................................................................................... 88 15. ORDERING INFORMATION .............................................................................................................. 89 16. REFERENCES .................................................................................................................................... 89 17. REVISION HISTORY ......................................................................................................................... 90 LIST OF FIGURES Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 12 Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 12 Figure 3.Control Port Timing - I²C Format ................................................................................................. 13 Figure 4.Control Port Timing - SPI Format ................................................................................................ 14 Figure 5.Typical Connection Diagram ....................................................................................................... 20 Figure 6.Full-Scale Analog Input ............................................................................................................... 21 Figure 7.Full-Scale Output ........................................................................................................................ 22 Figure 8.ATAPI Block Diagram (x = channel pair 1, 2, 3, 4) .....................................................................23 Figure 9.CS42528 Clock Generation ........................................................................................................ 25 Figure 10.I²S Serial Audio Formats ........................................................................................................... 29 Figure 11.Left-Justified Serial Audio Formats ........................................................................................... 30 Figure 12.Right-Justified Serial Audio Formats ......................................................................................... 30 Figure 13.One-Line Mode #1 Serial Audio Format ................................................................................... 31 Figure 14.One-Line Mode #2 Serial Audio Format ................................................................................... 31 Figure 15.ADCIN1/ADCIN2 Serial Audio Format ...................................................................................... 32 Figure 16.OLM Configuration #1 ............................................................................................................... 33 Figure 17.OLM Configuration #2 ............................................................................................................... 34 Figure 18.OLM Configuration #3 ............................................................................................................... 35 Figure 19.OLM Configuration #4 ............................................................................................................... 36 Figure 20.OLM Configuration #5 ............................................................................................................... 37 Figure 21.Control Port Timing in SPI Mode .............................................................................................. 38 Figure 22.Control Port Timing, I²C Write ................................................................................................... 39 Figure 23.Control Port Timing, I²C Read ................................................................................................... 39 Figure 24.Recommended Analog Input Buffer .......................................................................................... 73 Figure 25.Recommended Analog Output Buffer ....................................................................................... 73 Figure 26.Channel Status Data Buffer Structure ....................................................................................... 75 Figure 27.PLL Block Diagram ................................................................................................................... 77 Figure 28.Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 ............................................... 79 Figure 29.Jitter-Attenuation Characteristics of PLL - Configuration 3 ....................................................... 79 Figure 30.Recommended Layout Example ............................................................................................... 80 Figure 31.Consumer Input Circuit ............................................................................................................. 81 Figure 32.S/PDIF MUX Input Circuit ......................................................................................................... 81 Figure 33.TTL/CMOS Input Circuit ............................................................................................................ 81 Figure 34.Single-Speed Mode Stopband Rejection .................................................................................. 82 Figure 35.Single-Speed Mode Transition Band ........................................................................................ 82 Figure 36.Single-Speed Mode Transition Band (Detail) ............................................................................ 82 Figure 37.Single-Speed Mode Passband Ripple ...................................................................................... 82 Figure 38.Double-Speed Mode Stopband Rejection .................................................................................82 Figure 39.Double-Speed Mode Transition Band ....................................................................................... 82 Figure 40.Double-Speed Mode Transition Band (Detail) .......................................................................... 83 Figure 41.Double-Speed Mode Passband Ripple ..................................................................................... 83 |
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유사한 설명 - CS42528 |
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