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P3C1041 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Pyramid Semiconductor Corporation

๋ถ€ํ’ˆ๋ช… P3C1041
์ƒ์„ธ๋‚ด์šฉ  HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM
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์ œ์กฐ์‚ฌ  PYRAMID [Pyramid Semiconductor Corporation]
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P3C1041 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Pyramid Semiconductor Corporation

 
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P3C1041
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Document # SRAM130 REV OR
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE
OE
OE
OE
OE CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL not more negative than โ€“2.0V and
V
IH โ‰ค VCC + 0.5V, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ยฑ 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 1


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