CS5581

6

DS796A1

8/22/07

14:46

SWITCHING CHARACTERISTICS

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

8. Reset must not be released until the power supplies and the voltage reference are within specification.

9. CAL must remain high until RDY falls at the end of the calibration time.

10. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration

will be performed. CAL must remain high until RDY falls.

11. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

12. If CONV is held low continuously, conversions occur every 80 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 82 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 84 MCLKs.

RDY falls at the end of conversion.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Internal Oscillator

External Clock

XIN

12

0.5

14

16

16

16.2

MHz

MHz

Master Clock Duty Cycle

40

-

60

%

Reset

RST Low Time

(Note 8)

1-

-

µs

RST rising to RDY falling

Internal Oscillator

External Clock

-

-

120

1536

-

-

µs

MCLKs

Calibration

CAL pulse width

(Note 9, 10)

4-

-

MCLKs

CAL high setup time to RST rising

(Note 9, 10)

0-

-

ns

Calibration Time

RST rising (CAL high) to RDY falling

-

85218

-

MCLKs

Calibration Time

CAL rising (RST high) to RDY falling

-

85218

-

MCLKs

Conversion

CONV Pulse Width

4-

-

MCLKs

BP/UP setup to CONV falling

(Note 11)

0-

-

ns

CONV low to start of conversion

--

2

MCLKs

Perform Single Conversion (CONV high before RDY falling)

20

-

-

MCLKs

Conversion Time

(Note 12)

Start of Conversion to RDY falling

-

-

84

MCLKs