전자부품 데이터시트 검색엔진 |
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SI5323 데이터시트(PDF) 8 Page - Silicon Laboratories |
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SI5323 데이터시트(HTML) 8 Page - Silicon Laboratories |
8 / 16 page Si5323 8 Preliminary Rev. 0.2 5, 10, 32 VDD VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should be placed as close to device as is practical. 7 6 XB XA IAnalog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. If external reference is used, apply reference clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pin. 8, 31 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. 9 AUTOSEL I 3-Level Manual/Automatic Clock Selection. Three level input that selects the method of input clock selec- tion to be used. L = Manual M = Automatic non-revertive H = Automatic revertive 11 15 RATE0 RATE1 I 3-Level External Crystal or Reference Clock Rate. Three level input that selects the type and rate of external crystal or reference clock to be applied to the XA/XB port. RATE[1:0] LM = 38.88 MHz external clock MM = 114.285 MHz 3rd OT Crystal HH = Converts part to Si5322 All Others = Reserved 12 13 CKIN2+ CKIN2– I Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. 14 DBL2_BY I 3-Level Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled M = CKOUT2 disabled H = Bypass mode with CKOUT2 enabled Table 3. Si5323 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description |
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