HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1112/1122 Series

Seiko Instruments Inc.

15

3. Shutdown pin (ON/OFF pin)

This pin starts and stops the regulator.

When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-

in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially

resistance of several M

Ω between the VOUT pin and VSS pin.

The structure of the ON/OFF pin is as shown in Figure 13. Since the ON/OFF pin is neither pulled down

nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption

used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.

Table 8

Logic Type

ON/OFF Pin

Internal Circuits

VOUT Pin Voltage

Current Consumption

A

“L”: Power on

Operating

Set value

A

“H”: Power off

Stopped

B

“L”: Power off

Stopped

B

“H”: Power on

Operating

Set value

VSS

ON/OFF

VIN

Figure 13

The S-1112/1122 Series requires an output capacitor between the VOUT and VSS pins for phase

compensation. A ceramic capacitor with a capacitance of 0.47

µF or more can be used. Even if using an OS

capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a capacitance of 0.47

µF or more and an ESR

of 10

Ω or less are required.

The value of the output overshoot or undershoot transient response varies depending on the value of the output

capacitor.

When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature

characteristics, on the actual device.