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CAT24WC03UTE13 데이터시트(PDF) 6 Page - Catalyst Semiconductor

부품명 CAT24WC03UTE13
상세설명  2K/4K-Bit Serial EEPROM with Partial Array Write Protection
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제조업체  CATALYST [Catalyst Semiconductor]
홈페이지  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24WC03UTE13 데이터시트(HTML) 6 Page - Catalyst Semiconductor

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Discontinued
Parts
CAT24WC03/05
6
Doc. No. 1005, Rev. F
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The CAT24WC03/05 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiving
each 8-bit byte.
When the CAT24WC03/05 is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24WC03/05 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/
W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC03/05. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24WC03/05 acknowledge once more
and the Master generates the STOP condition, at which
time the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC03/05 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
Page Write operation is initiated in the same manner as
the Byte Write operation; however, instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, the CAT24WC03/05 will respond with
an acknowledge and internally increment the low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC03/05 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC03/05 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC03/05 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Figure 7. Page Write Timing
BYTE
ADDRESS
SLAVE
ADDRESS
S
DATA
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+P
BYTE
ADDRESS (n)
A
C
K
A
C
K
DATA n
A
C
K
S
T
O
P
S
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0


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