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74AUP1G74 데이터시트(PDF) 4 Page - NXP Semiconductors |
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4 / 23 page 74AUP1G74_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 01 — 25 August 2006 4 of 23 Philips Semiconductors 74AUP1G74 Low-power D-type flip-flop with set and reset; positive-edge trigger 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care. 8. Limiting values Table 3. Pin description Symbol Pin Description SOT765-1 and SOT833-1 SOT902-1 CP 1 7 clock input (LOW-to-HIGH, edge triggered) D 2 6 data input Q 3 5 complement flip-flop output GND 4 4 ground (0 V) Q 5 3 true flip-flop output RD 6 2 asynchronous reset-direct (active LOW) SD 7 1 asynchronous set-direct (active LOW) VCC 8 8 supply voltage Table 4. Asynchronous operation[1] Input Output SD RD CP D Q Q L H XXH L H L XXL H L L XXH H Table 5. Synchronous operation[1] Input Output SD RD CP D Qn+1 Qn+1 HH ↑ LLH HH ↑ HHL Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V IIK input clamping current VI <0V - −50 mA VI input voltage [1] −0.5 +4.6 V IOK output clamping current VO <0V - −50 mA VO output voltage Active mode and Power-down mode [1] −0.5 +4.6 V IO output current VO =0 VtoVCC - ±20 mA ICC supply current - +50 mA |
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