tm

April 2007

©1994 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHC273 Rev. 1.5

74VHC273

Octal D-Type Flip-Flop

Features

General Description

The VHC273 is an advanced high speed CMOS Octal

D-type flip-flop fabricated with silicon gate CMOS tech-

nology. It achieves the high speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

The register has a common buffered Clock (CP) which is

fully edge-triggered. The state of each D input, one setup

time before the LOW-to-HIGH clock transition, is trans-

ferred to the corresponding flip-flop's Q output. The

Master Reset (MR) input will clear all flip-flops simulta-

neously. All outputs will be forced LOW independently of

Clock or Data inputs by a LOW voltage level on the MR

input.

An input protection circuit insures that 0V to 7V can be

applied to the inputs pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Order Number

Package

Number

Package Description

74VHC273M

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC273SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC273BQ

(Preliminary)

MLP020B

(Preliminary)

20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 4.5mm

74VHC273MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide