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ML145152 데이터시트(PDF) 11 Page - LANSDALE Semiconductor Inc. |
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ML145152 데이터시트(HTML) 11 Page - LANSDALE Semiconductor Inc. |
11 / 35 page www.lansdale.com Page 11 of 35 Issue A LANSDALE Semiconductor, Inc. ML145155 ML145155 TYPICAL APPLICATIONS Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface fin 3 LED DISPLAY MC14489 KEYBOARD CMOS MPU/MCU ENB CLK DATA 1/2 MC1458* ML145155 MC120xx PRESCALER UHF/VHF TUNER OR CATV FRONT END 4.0 MHz φV φR + – * The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page for additional information.The φR and φV outputs swing rail–to–rail.Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. OUTPUT PINS PDout Phase Detector A Output (PDIP, SOG – Pin 6) Three–state output of phase detector for use as loop error signal. Double–ended outputs are also available for this pur- pose (see φV and φR). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High–Imped- ance State φR, φV Phase Detector B Outputs (PDIP, SOG – Pins 4, 3) These phase detector outputs can be combined externally for a loop–error signal. A single–ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by fV pulsing low. fR remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by fR pulsing low. fV remains essentially high. If the frequency of fV = fR and both are in phase, then both fV and fR remain high except for a small minimum time peri- od when both pulse low in phase. LD Lock Detector Output (PDIP – Pin 8, SOG – Pin 9) Essentially a high level when loop is locked (fR, fV of same phase and frequency). LD pulses low when loop is out of lock. SW1, SW2 Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15) SW1 and SW2 provide latched open–drain outputs corre- sponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as 15 V, independent of the VDD supply voltage. These are typically used for band switch functions. A logic 1 causes the output to assume a high–impedance state, while a logic 0 causes the out- put to be low. REFout Buffered Reference Oscillator Output (PDIP, SOG – Pin 15) Buffered output of on–chip reference oscillator or externally provided reference–input signal. POWER SUPPLY VDD Positive Power Supply (PDIP, SOG – Pin 5) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (PDIP, SOG – Pin 7) The most negative supply potential. This pin is usually ground. |
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