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SM80952 데이터시트(PDF) 4 Page - SyncMOS Technologies,Inc

부품명 SM80952
상세설명  8 - Bit Micro-controller with 4/8KB ROM embedded
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제조업체  SYNCMOS [SyncMOS Technologies,Inc]
홈페이지  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

SM80952 데이터시트(HTML) 4 Page - SyncMOS Technologies,Inc

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May 2001
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
SM8051/80952
Pin Descriptions
40L
PDIP
Pin#
44L
QFP
Pin#
44L
PLCC
Pin#
Symbol
Active
I/O
Names
1
40
2
P1.0
i/o bit 0 of port 1
2
41
3
P1.1
i/o bit 1 of port 1
3
42
4
P1.2
i/o bit 2 of port 1
4
43
5
P1.3
i/o bit 3 of port 1
5
44
6
P1.4
i/o bit 4 of port 1
6
1
7
P1.5
i/o bit 5 of port 1
7
2
8
P1.6
i/o bit 6 of port 1
8
3
9
P1.7
i/o bit 7 of port 1
9
4
10
RES
H
i Reset
10
5
11
RXD/P3.0
i/o Receive data & bit 0 of port 3
11
7
13
TXD/P3.1
i/o Transmit data & bit 1 of port 3
12
8
14
#INT0/P3.2
L/ -
i/o low true interrupt 0 & bit 2 of port 3
13
9
15
#INT1/P3.3
L/ -
i/o low true interrupt 1 & bit 3 of port 3
14
10
16
T0/P3.4
i/o Timer 0 & bit 4 of port 3
15
11
17
T1/P3.5
i/o Timer 1 & bit 5 of port 3
16
12
18
#WR/P3.6
L/ -
i/o external memory write & bit 6 of port 3
17
13
19
#RD/P3.7
L/ -
i/o external memory read & bit 7 of port 3
18
14
20
XTAL2
o Crystal out
19
15
21
XTAL1
i Crystal in
20
16
22
VSS
Sink Voltage, Ground
21
18
24
P2.0/A8
i/o bit 0 of port 2 & bit 8 of external memory address
22
19
25
P2.1/A9
i/o bit 1 of port 2 & bit 9 of external memory address
23
20
26
P2.2/A10
i/o bit 2 of port 2 & bit 10 of external memory address
24
21
27
P2.3/A11
i/o bit 3 of port 2 & bit 11 of external memory address
25
22
28
P2.4/A12
i/o bit 4 of port 2 & bit 12 of external memory address
26
23
29
P2.5/A13
i/o bit 5 of port 2 & bit 13 of external memory address
27
24
30
P2.6/A14
i/o bit 6 of port 2 & bit 14 of external memory address
28
25
31
P2.7/A15
i/o bit 7 of port 2 & bit 15 of external memory address
29
26
32
#PSEN
L
o program storage enable
30
27
33
ALE
-
o address latch enable
31
29
35
#EA
L
i external access
32
30
36
P0.7/AD7
i/o bit 7 of port 0 & data/address bit 7 of external memory
33
31
37
P0.6/AD6
i/o bit 6 of port 0 & data/address bit 6 of external memory
34
32
38
P0.5/AD5
i/o bit 5 of port 0 & data/address bit 5 of external memory
35
33
39
P0.4/AD4
i/o bit 4 of port 0 & data/address bit 4 of external memory
36
34
40
P0.3/AD3
i/o bit 3 of port 0 & data/address bit 3 of external memory
37
35
41
P0.2/AD2
i/o bit 2 of port 0 & data/address bit 2 of external memory
38
36
42
P0.1/AD1
i/o bit 1 of port 0 & data/address bit 1 of external memory
39
37
43
P0.0/AD0
i/o bit 0 of port 0 & data/address bit 0 of external memory
40
38
44
VDD
Drive Voltage, +5 Vcc


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