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CDCUA877ZQL 데이터시트(PDF) 6 Page - Texas Instruments

부품명 CDCUA877ZQL
상세설명  1.8-V PHASE LOCK LOOP CLOCK DRIVER
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ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
CDCUA877
SCAS769A – AUGUST 2006 – REVISED JUNE 2007
over recommended operating free-air temperature range
AVDD,
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VDDG
VIK
Input (cl inputs)
II = –18 mA
1.7 V
–1.2
V
IOH = -100 =A
1.7 V to 1.9 V
VDDQ
– 0.2
VOH
High-level output voltage
V
IOH = –9 mA
1.7 V
1.1
IOL = 100 μA
0.1
VOL
Low-level output voltage
V
IOL = 9 mA
1.7 V
0.6
IO(DL) Low-level output current, disabled
VO(DL) = 100 mV, OE = L
1.7 V
100
μA
VOD
Differential output voltage(1)
1.7 V
0.5
V
CK, CK
1.9 V
±250
II
Input current
μA
OE, OS, FBIN,
1.9 V
±10
FBIN
IDD(L
CK and CK = L
1.9 V
500
Supply current, static (IDDQ + IADD)
μA
D)
CK and CK = 410 MHz,
All outputs are open
1.9 V
225
mA
(not connected to a PCB)
Supply current, dynamic ( IDDQ + IADD)
IDD
(see (2) for CPD calculation)
All outputs are loaded with 2 pF
and 120-
Ω termination resistor,
1.9 V
225
mA
CK and CK = 410 MHz
CK, CK
VI = VDD or GND
1.8 V
2
3
CI
Input capacitance
pF
FBIN, FBIN
VI = VDD or GND
1.8 V
2
3
CK, CK
VI = VDD or GND
1.8 V
0.25
Change in input
CI(Δ)
pF
current
FBIN, FBIN
VI = VDD or GND
1.8 V
0.25
(1)
VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 10 for a definition.
(2)
Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the
power supply, and CPD is the power dissipation capacitance.
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Clock frequency (operating)(1) (2)
AVDD, VDD = 1.8 V ±0.1 V
125
410
MHz
fCK
Clock frequency (application)(1) (3)
AVDD, VDD = 1.8 V ±0.1 V
160
410
MHz
tDC
Duty cycle, input clock
AVDD, VDD = 1.8 V ±0.1 V
40%
60%
tL
Stabilization time(4)
AVDD, VDD = 1.8 V ±0.1 V
6
μs
(1)
The PLL must be able to handle spread spectrum induced skew.
(2)
Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other
timing parameters (used for low speed system debug).
(3)
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
(4)
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,
within the value specified by the static phase offset t(φ), after power up. During normal operation, the stabilization time is also the time
required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic
low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven
low for one complete clock cycle.
6
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