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TMP19A64F20AXBG 데이터시트(PDF) 4 Page - Toshiba Semiconductor |
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TMP19A64F20AXBG 데이터시트(HTML) 4 Page - Toshiba Semiconductor |
4 / 64 page TMP19A64F20AXBG TMP19A64(rev1.0)1-2 • Almost all instructions can be executed with one clock. • High performance is possible via a three-operand operation instruction. • 5-stage pipeline • Built-in high-speed memory • DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock. Low power consumption • Optimized design using a low power consumption library • Standby function that stops the operation of the processor core 3) High-speed interrupt response suitable for real-time control • Independency of the entry address • Automatic generation of factor-specific vector addresses • Automatic update of interrupt mask levels (2) On Chip program memory and data memory Product name On chip ROM On chip RAM TMP19A64F20AXBG 2 Mbytes (Flash) 64 Kbytes TMP19A64C1DXBG 1.5 Mbytes 56 Kbytes • ROM correction function: 1 word × 8 blocks, 8 words × 4 blocks • Backup RAM: 512 bytes (3) External memory expansion • 16-Mbyte off-chip address for code and date • External data bus: Separate bus/multiplexed bus : Dynamic bus sizing for 8- and 16-bit widths ports. • Chip select/wait controller : 6 channels (4) DMA controller : 8 channels • Data to be transferred to internal memory, internal I/O, external memory, and external I/O (5) 16-bit timer : 11 channels • 16-bit interval timer mode • 16-bit event counter mode • 16-bit PPG output • Event capture function • 2-phase pulse input counter function (1 channel assigned to perform this function): Multiplication-by-4 mode (6) 32-bit timer • 32-bit input capture register : 4 channels • 32-bit compare register : 10 channels • 32-bit time base timer : 1 channel (7) Clock timer : 1 channel (8) General-purpose serial interface: 7 channels • Either UART mode or synchronous mode can be selected. (9) Serial bus interface : 1 channel • Either I 2C bus mode or clock synchronous mode can be selected |
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