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TC9WMB2AFU 데이터시트(PDF) 9 Page - Toshiba Semiconductor

부품명 TC9WMB2AFU
상세설명  CMOS Digital Integrated Circuits Silicon Monolithic
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC9WMB1AFK/FU,TC9WMB2AFK/FU
2007-10-19
9
(b) If a start condition is issued while the device is receiving a write instruction (device address,
R/W, address, and data), this write instruction is discarded and the next instruction is accepted.
(A byte write is given below as an example. This is the same as a page write.)
(c) If a stop condition is issued while the device is receiving a write instruction (device address,
R/W, address, and data), the device enters the standby state. However, the device ignores the
stop condition while sending an acknowledge signal after it receives the D0 bit. (A write
operation starts.)
(A byte write is given below as an example. This is the same as a page write.)
(d) No instruction is accepted while a write operation is in progress (after a stop condition for a
write instruction is received).
(The device does not receive a start or stop condition during this time.)
(5)
Read operation
(a) The address counter is incremented when a read instruction is received successfully. It is
incremented on the falling edge of the SCL pulse where the least significant bit of data is
driven.
(b) If a start condition is issued while the device is receiving a read instruction (device address,
R/W, address, or data), this read instruction is discarded and the next instruction is accepted. (A
start condition is accepted even during data transfer.)
(A current address read is given below as an example. This is the same as the other read
modes.
)
Incremented.
Start
Device address
R/W
ACK
Address
ACK
Data
ACK
Stop
Write instruction
Address counter is not incremented during this period.
Incremented.
Start
Device address
R/W
ACK
Address
ACK
Data
ACK
Stop
Write instruction
Address counter is not incremented during this period.
A write operation starts.
Incremented.
Start
Device address
R/W
ACK
Data
NACK Stop
Read instruction
Address counter is not incremented during this period.
Increment
D1
D0
Figure 12 Increment Timing Diagram


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