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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TC59LM836DKB-40 데이터시트(PDF) 10 Page - Toshiba Semiconductor |
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TC59LM836DKB-40 데이터시트(HTML) 10 Page - Toshiba Semiconductor |
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10 / 65 page  TC59LM836DKB-30,-33,-40 2005-03-07 10/65 Rev 1.3 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued) -30 -33 -40 SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNIT NOTES tLZ Data-out Low Impedance Time from CLK −0.5 −0.5 −0.6 3, 6, 8 tHZ Data-out High Impedance Time from CLK 0.5 0.5 0.6 3, 7, 8 tQPDH Last output to PD High Hold Time 0 0 0 tPDEX Power Down Exit Time 0.6 0.6 0.7 3 tT Input Transition Time 0.1 1 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry −0.5 × tCK 5 −0.5 × tCK 5 −0.5 × tCK 5 ns 3 tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3.9 5 tPAUSE Pause Time after Power-up 200 200 200 µs CL = 4 5 5 5 CL = 5 6 6 6 IRC Random Read/Write Cycle Time (applicable to same bank) CL = 6 7 7 7 IRCD RDA/WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 4 4 4 4 CL = 5 5 5 5 IRAS LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 6 6 6 6 IRBD Random Bank Access Delay (applicable to other bank) 2 2 2 BL = 2 2 2 2 IRWD LAL following RDA to WRA Delay (applicable to other bank) BL = 4 3 3 3 IWRD LAL following WRA to RDA Delay (applicable to other bank) 1 1 1 CL = 4 7 7 7 CL = 5 7 7 7 IRSC Mode Register Set Cycle Time CL = 6 7 7 7 IPD PD Low to Inactive State of Input Buffer 2 2 2 IPDA PD High to Active State of Input Buffer 1 1 1 CL = 4 19 19 19 CL = 5 23 23 23 IPDV Power down mode valid from REF command CL = 6 25 25 25 CL = 4 19 19 19 CL = 5 23 23 23 IREFC Auto-Refresh Cycle Time CL = 6 25 25 25 ICKD REF Command to Clock Input Disable at Self-Refresh Entry IREFC IREFC IREFC ILOCK DLL Lock-on Time (applicable to RDA command) 200 200 200 cycle |
유사한 부품 번호 - TC59LM836DKB-40 |
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유사한 설명 - TC59LM836DKB-40 |
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