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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TC59LM836DKG-40 데이터시트(PDF) 9 Page - Toshiba Semiconductor |
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TC59LM836DKG-40 데이터시트(HTML) 9 Page - Toshiba Semiconductor |
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9 / 65 page  TC59LM836DKG-30,-33,-40 2005-03-07 9/65 Rev 1.3 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (VDD = 2.5 ± 0.125V, VDDQ = 1.4 ∼ 1.9V, TCASE = 0 ∼ 85°C) -30 -33 -40 SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNIT NOTES tRC Random Cycle Time 20.0 22.5 25 3 CL = 4 4.0 5.0 4.5 7.5 5.0 7.5 3 CL = 5 3.5 5.0 3.75 7.5 4.5 7.5 3 tCK Clock Cycle Time CL = 6 3.0 5.0 3.33 7.5 4.0 7.5 3 tRAC Random Access Time 20.0 22.5 25 3 tCH Clock High Time 0.45 × tCK 0.45 × tCK 0.45 × tCK 3 tCL Clock Low Time 0.45 × tCK 0.45 × tCK 0.45 × tCK 3 tCKQS QS Access Time from CLK −0.45 0.45 −0.45 0.45 −0.5 0.5 3, 8,10 tQSQ Data Output Skew from QS 0.2 0.25 0.3 tQSQA Data Output Skew from QS to All DQ 0.3 0.35 0.4 tAC Data Access Time from CLK −0.5 0.5 −0.5 0. 5 −0.6 0.6 3, 8,10 tOH Data Output Hold Time from CLK −0.5 0.5 −0.5 0.5 −0.6 0.6 3, 8 tHP CLK half period (minimum of Actual tCH, tCL) min(tCH, tCL) min(tCH, tCL) min(tCH, tCL) 3 tQSP QS (read) Pulse Width tHP− tQHS tHP− tQHS tHP− tQHS 4, 8 tQSQV Data Output Valid Time from QS tHP− tQHS tHP− tQHS tHP− tQHS 4, 8 tQHS DQ, QS Hold Skew factor 0.055 × tCK + 0.17 0.055 × tCK + 0.17 0.055 × tCK + 0.17 tDQSS DS (write) Low to High Setup Time 0.8 ×tCK 1.2 ×tCK 0.8 ×tCK 1.2 ×tCK 0.8 ×tCK 1.2 ×tCK 3 tDSPRE DS (write) Preamble Pulse Width 0.4 ×tCK 0.4 ×tCK 0.4 ×tCK 4 tDSPRES DS First Input Setup Time 0 0 0 3 tDSPREH DS First Low Input Hold Time 0.3 ×tCK 0.3 ×tCK 0.3 ×tCK 3 tDSP DS High or Low Input Pulse Width 0.45 ×tCK 0.55 ×tCK 0.45 ×tCK 0.55 ×tCK 0.45 ×tCK 0.55 ×tCK 4 CL = 4 0.75 0.8 1.0 3, 4 CL = 5 0.75 0.8 1.0 3, 4 tDSS DS Input Falling Edge to Clock Setup Time CL = 6 0.75 0.8 1.0 3, 4 tDSPST DS (write) Postamble Pulse Width 0.45 × tCK 0.45 × tCK 0.45 × tCK 4 CL = 4 0.75 0.8 1.0 3, 4 CL = 5 0.75 0.8 1.0 3, 4 tDSPSTH DS (write) Postamble Hold Time CL = 6 0.75 0.8 1.0 3, 4 tDSSK UDS – LDS Skew −0.4 × tCK 0.4 × tCK −0.4 × tCK 0.4 × tCK −0.4 × tCK 0.4 × tCK tDS Data Input Setup Time from DS 0.3 0.35 0.4 4, 11 tDH Data Input Hold Time from DS 0.3 0.35 0.4 4, 11 tIS Command/Address Input Setup Time 0.6 0.6 0.7 3 tIH Command/Address Input Hold Time 0.6 0.6 0.7 ns 3 |
유사한 부품 번호 - TC59LM836DKG-40 |
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유사한 설명 - TC59LM836DKG-40 |
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