전자부품 데이터시트 검색엔진 |
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TC59LM914AMG-50 데이터시트(PDF) 7 Page - Toshiba Semiconductor |
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TC59LM914AMG-50 데이터시트(HTML) 7 Page - Toshiba Semiconductor |
7 / 59 page TC59LM914/06AMG-37,-50 2004-08-20 7/59 Rev 1.0 RECOMMENDED DC OPERATING CONDITIONS (VDD=2.5V ± 0.125V, VDDQ=1.4V ~ 1.9V, TCASE = 0~85°C) MAX SYMBOL PARAMETER -37 -50 UNIT NOTES IDD1S Operating Current tCK = min, IRC = min ; Read/Write command cycling ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; 1 bank operation, Burst length = 4 ; Address change up to 2 times during minimum IRC. 280 240 1, 2 IDD2N Standby Current tCK = min, CS = VIH, PD = VIH ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; All banks: inactive state ; Other input signals are changed one time during 4 × tCK. 120 100 1, 2 IDD2P Standby (Power Down) Current tCK = min, CS = VIH, PD = VIL (Power Down) ; 0 V ≤ VIN ≤ VDDQ ; All banks: inactive state 90 80 1, 2 IDD4W Write Operating Current (4 Banks) 8 Bank Interleaved continuos burst wirte operation ; tCK = min, IRC = min Burst Length = 4, CAS Latency = 5 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Address inputs change once per clock cycle ; DQ and DQS inputs change twice per clock cycle. 450 350 1, 2 IDD4R Read Operating Current (4 Banks) 8 Bank Interleaved continuos burst wirte operation ; tCK = min, IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 5 ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Address inputs change once per clock cycle ; Read data change twice per clock cycle. 450 350 1, 2 IDD5B Burst Auto Refresh Current Refresh command at every IREFC at interval ; tCK = min、IREFC = min CAS Latency = 5 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Address inputs change up to 2 times during minimum IREFC. DQ and DQS inputs change twice per clock cycle. 280 250 1, 2, 3 IDD6 Self-Refresh Current Self-Refresh mode PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ 20 20 mA 2 Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters define the current between VDD and VSS. 3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet tREFI specification. |
유사한 부품 번호 - TC59LM914AMG-50 |
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유사한 설명 - TC59LM914AMG-50 |
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