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TC74HC40103AP 데이터시트(PDF) 5 Page - Toshiba Semiconductor |
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TC74HC40103AP 데이터시트(HTML) 5 Page - Toshiba Semiconductor |
5 / 14 page TC74HC40102,40103AP/AF 2007-10-01 5 Logic Diagram Inputs Output CLR APE SPE J TE CK Q H X X X X X L L H H H H X H L H H L H X L L L H H X H L L H L X L L L L X L Qn L L L X L Qn L L L X H X Qn Function Description The TC74HC40102A and TC74HC40103A are 8-stage presettable synchronous down counters. Carry Out/Zero Detect ( CO/ZD ) is output at the “L” level for the period of 1 bit when the readout becomes “0”. The TC74HC40102A adopts binary coded decimal notation, making setting up to 99 counts possible. While the TC74HC40103A adopts 8-bit binary counter and can set up to 255 counts. Count Operation At the “H” level of control input of CLR , SPE and APE , the counter carries out down count operation one by one at the rise of pulse given to CK input. Count operation can be inhibited by setting Carry Input/clock Enable ( CI/CE ) to the “H” level. CO/ZD is output at the “L” level when the readout becomes “0”, but is not output even if the readout becomes “0” when CI/CE is at the “H” level, thus maintaining the “H” level. Synchronous cascade operation can be carried out by using CI/CE input and CO/ZD output. The contents of count jump to maximum count (99 for the TC74HC40102A and 255 for the TC74HC40103A) if clock is given when the readout is “0”. Therefore, operation of 100-frequency division and that of 256-frequency division are carried out for the TC74HC40102A and TC74HC40103A, respectively, when clock input alone is given without various kinds of preset operation. |
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