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TLP512 데이터시트(PDF) 4 Page - Toshiba Semiconductor |
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TLP512 데이터시트(HTML) 4 Page - Toshiba Semiconductor |
4 / 7 page TLP512 2007-10-01 4 Switching Characteristics (Ta = 25°C) Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Propagation delay time (H → L) tpHL IF = 0 → 16 mA, RL = 1.9 kΩ ⎯ ⎯ 0.8 μs Propagation delay time (L → H) tpLH 1 IF = 16 → 0 mA, RL = 1.9 kΩ ⎯ ⎯ 0.8 μs Common mode transient immunity at logic high output (Note 8) CMH IF = 0 mA, VCM = 200 VP−P RL = 1.9 kΩ ⎯ 1500 ⎯ V/ μs Common mode transient immunity at logic low output (Note 8) CML 2 IF = 16 mA, VCM = 200 VP−P RL = 1.9 kΩ ⎯ −1500 ⎯ V/ μs Note 8: Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (VOUT > 2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse, VCM, to assure that the output will remain in a logic low state (VOUT < 0.8 V). Note 9: Electrostatic discharge immunity (pin to pin): 100 V (max) (C ≤ 200 pF, R = 0) Test Circuit 1: Switching Time Test Circuit Test Circuit 2: Common Mode Noise Immunity Test Circuit s) ( f t (V) 160 L CM , s) ( r t (V) 160 H CM μ = μ = 1 3 6 4 2 5 VCC = 5 V VO Output monitor IF RL VCM Pulse generator ZO = 50 Ω VCM 200 V VO (IF = 0 mA) VO (IF = 16 mA) 0 V 5 V 2 V 0.8 V VOL 10% 90% tf tr tpHL 1.5 V 5 V 1.5 V VOL tpLH VO 0 IF 1 3 6 4 2 5 VCC = 5 V VO Output monitor Pulse input PW = 100 μs Duty ratio = 1/10 IF monitor IF RL |
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