전자부품 데이터시트 검색엔진 |
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74LVCE161284DGGRG4 데이터시트(PDF) 8 Page - Texas Instruments |
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74LVCE161284DGGRG4 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 16 page www.ti.com PARAMETER MEASUREMENT INFORMATION Output (see Note C) From B or Y Output Under Test SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT VOLTAGE WAVEFORMS MEASURED AT TP1 SLEW RATE WAVEFORMS (B1−8 AND Y9−13) 62 Ω CL = 50 pF (see Note A) TP1 VCC CABLE CL = 50 pF (see Note A) Sink Load Source Load 62 Ω A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN) OR PERI LOGIC IN TO PERI LOGIC OUT VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE 2.7 V VOH VOL 0 V 1.4 V 1.4 V 2 V 2 V 0.8 V 0.8 V tr tf TP1 From B or Y Output CL = 50 pF (see Note A) 500 Ω VCC CABLE NOTES: A. CL includes probe and jig capacitance. B. When VCC CABLE is 3.3 V " 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and 1.9 V for the falling edge. When VCC CABLE is 5 V " 0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge and between 95% VCC CABLE and 50% VCC CABLE for the falling edge. C. Input rise (tr) and fall (tf) times are 3 ns. Rise and fall times (open drain) are <120 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Input (see Note C) 0 V 2.7 V Input (see Note B) Output (see Note B) Output (see Note B) tf1 95% (VCC CABLE = 5.0 V"0.5 V) 50% (VCC CABLE = 5.0 V"0.5 V) 1.9 V (VCC CABLE = 5.0 V"0.5 V) 0.4 V tr1 t slew fall + VCC 95% – 50% t f1 t slew rise + 1.9 V – 0.4 V t r1 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES541 – JANUARY 2004 – REVISED MARCH 2005 Figure 2. Load Circuits and Voltage Waveforms 8 |
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