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74AC573B 데이터시트(PDF) 1 Page - STMicroelectronics |
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74AC573B 데이터시트(HTML) 1 Page - STMicroelectronics |
1 / 11 page 1/11 April 2001 s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level, the outputs will be in a high impedance state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74AC573B SOP 74AC573M 74AC573MTR TSSOP 74AC573TTR TSSOP DIP SOP |
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