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S-1131B50UA-N5JTFG 데이터시트(PDF) 9 Page - Seiko Instruments Inc |
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S-1131B50UA-N5JTFG 데이터시트(HTML) 9 Page - Seiko Instruments Inc |
9 / 29 page HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR Rev.3.0_01 S-1131 Series Seiko Instruments Inc. 9 Standard Circuit ON/OFF *2 VSS VOUT VIN CIN *1 CL *3 Input Output GND Single GND *1. CIN is a capacitor for stabilizing the input. *2. In case of product with shutdown function. *3. A tantalum capacitor (2.2 µF or more) can be used. Figure 11 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Application Conditions Input capacitor (CIN): 1.0 µF or more Output capacitor (CL): 2.2 µF or more (tantalum capacitor) Caution A general series regulator may oscillate, depending on the external components selected. Check that no oscillation occurs with the application using the above capacitor. |
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