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S-80146CNMC-JK7T2G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 14 Page - Seiko Instruments Inc

๋ถ€ํ’ˆ๋ช… S-80146CNMC-JK7T2G
์ƒ์„ธ๋‚ด์šฉ  ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (INTERNAL DELAY TIME SETTING)
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์ œ์กฐ์‚ฌ  SII [Seiko Instruments Inc]
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ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (INTERNAL DELAY TIME SETTING)
S-801 Series
Rev.3.3_00
14
Seiko Instruments Inc.
Operation
1. Basic Operation: CMOS Output (Active Low)
1-1. When the power supply voltage (VDD) is higher than the release voltage (+VDET), the Nch
transistor is OFF and the Pch transistor is ON to provide VDD (high) at the output. Since the
Nch transistor N1 in Figure 10 is OFF, the comparator input voltage is
C
B
A
DD
C
B
R
R
R
V
)
R
R
(
+
+
โ€ข
+
.
1-2. When the VDD goes below +VDET, the output provides the VDD level, as long as VDD remains
above the detection voltage (โ€“VDET). When the VDD falls below โ€“VDET (point A in Figure 11),
the Nch transistor becomes ON, the Pch transistor becomes OFF, and the VSS level appears
at the output. At this time the Nch transistor N1 in Figure 10 becomes ON, the comparator
input voltage is changed to
B
A
DD
B
R
R
V
R
+
โ€ข
.
1-3. When the VDD falls below the minimum operating voltage, the output becomes undefined, or
goes to VDD when the output is pulled up to VDD.
1-4. The VSS level appears when VDD rises above the minimum operating voltage. The VSS level still
appears even when VDD surpasses the โ€“VDET, as long as it does not exceed the release
voltage
+V
DET.
1-5. When VDD rises above +VDET (point B in Figure 11), the Nch transistor becomes OFF and the
Pch transistor becomes ON to provide VDD at the output. The VDD at the OUT pin is delayed for
tD due to the delay circuit.
*1
DS
*1
RC
RB
Pch
Nch
VREF
VDD
+
โˆ’
RA
N1
VSS
OUT
Delay circuit
*1. Paracitic diode
Figure 10 Operation 1


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