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S-80144BLPF-JE5TFG 데이터시트(PDF) 15 Page - Seiko Instruments Inc |
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S-80144BLPF-JE5TFG 데이터시트(HTML) 15 Page - Seiko Instruments Inc |
15 / 33 page ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (INTERNAL DELAY TIME SETTING) Rev.3.3_00 S-801 Series Seiko Instruments Inc. 15 A B VDD tD VSS Minimum operating voltage Output from OUT pin VDD VSS (1) (2) (3) (5) (4) Hysterisis width (VHYS) Release voltage ( +V DET) Detection voltage ( −V DET) Figure 11 Operation 2 2. Delay Circuit 2-1. Delay Time The delay circuit delays the output signal from the time at which the power voltage (VDD) exceeds the release voltage ( +V DET) when VDD is turned on. The output signal is not delayed when the VDD goes below the detection voltage (–VDET). (Refer to Figure 11.) The delay time (tD) is a fixed value that is determined by a built-in oscillation circuit and counter. 2-2. DS Pin (ON/OFF Switch Pin for Delay Time) The DS pin should be connected to Low or High. When the DS pin is High, the output delay time becomes short since the output signal is taken from the middle of counter circuit (Refer to Figure 16). 3. Other Characteristics 3-1. Temperature Characteristics of Detection Voltage The shaded area in Figure 12 shows the temperature characteristics of the detection voltage. –40 25 +0.792 mV/°C 2.200 85 Ta [ °C] –0.792 mV/ °C –VDET [V] Figure 12 Temperature Characteristics of Detection Voltage (Example for S-80122xxxx) |
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