active power distribution. Since the power distribu-

tion serves as the well ties the inherent capacitance

of the reversed biased well junctions is closely

coupled into the power distribution and functions as

localized decoupling capacitance helping to keep

high frequency noise from being coupled from one

macro to the other through the power distribution.

The salicided active local distribution of the DOU-

BLE BUFFER cell is supplied its power by a screen

grid of power bused on both second and third metal.

The second metal buses run every nine cells and

are two wiring tracks wide. Vss and Vdd is inter-

leaved every other bus. The third level buses run

every thirty six tracks and are three tracks wide. This

grid is sufficient to power all but the largest arrays

though the use of custom structured cores or gate

counts above 500,000 usable cells along with high

clock rates may result in the need for supplemental

power. The overall die power distribution is broken

down into a minimum of three Vdd and three Vss

distributions. Optionally other distributions for spe-

cialized I/O may be inserted. The standard distribu-

tions are Internal Vdd and Vss, serving the internal

cells and the prebuffer sections of the I/O, External

Vdd and Vss serving the output transistors only, and

Receiver Vdd and Vss serving the first stages of the

receiver cells. Optional distributions for 5.0V inter-

face, GTL, CTL, and other standards can be utilized

as necessary.

LIBRARY

The following section details the elements which

make up the ISB35000 Series library. The elements

are organised into three categories:

1. Macrocell library with Input, Output, Bidirectional

Buffers including JTAG macrocells and Core

cells.

2. Macrofunctions

3. Module generators

4. Embedded Functions

I/O BUFFERS

ISB35000 technology does not utilize a standard

type I/O cell but is a leader in the emerging Sea of

I/O approach to handling the chip interface problem.

This approach starts at the bond pad area of the I/O

where the pad size and pitch is not determined until

the customers choice of packaging, signal interface

standards and I/O count is considered. Wire bond

pad spacings for 80 micron centres are available

where large signal counts are most important.

Pad spacing can be increased incrementally. It is

expected that most designs will use 100 or 120

micron spacings. It is also possible to use different

spacings for different width output sections when

needed within the same device.

Along with the variable bond pad spacing the I/O

output transistor section does not have a fixed

width. Previous technologies utilized a design ap-

proach where the desired full function buffer was

designed for a maximum current taking one pad

location with the usual current in the range of twenty

four milliamps. The approach followed in ISB35000

is to have identical twenty micron wide output tran-

sistor slices stepped around the die. Each slice

contains one set of protection diodes to the external

power rails and eight P and eight N transistors. The

transistors are specifically laid out and selectively

non salicided for ESD protection and latch up pre-

vention. These slices are paralleled to meet the

current needs of the user, for example, to construct

a 24mA sink and 12mA source LVTTL buffer, a

number of slices would be used. The next group of

devices that makes up the I/O circuits is again a 20

u wide slice of specialized transistors that are util-

ized to form the slew rate control sections of the I/O.

Each of these slices has circuits to control the

switching of up two sections of P and N output

transistors. These sections are of course created

from the output transistor slice above the slew rate

section and can be connected as desired by the

designer. Many configurations of circuits can be

created to supply the desired results with slew rate

slices paralleled with multiple output sections. A

further function of the scan circuits is current spike

suppression during switching of the I/O transistors.

The logic utilized causes the conducting transistors

to turn off before the opposing set of transistors turn

on.

Inside the slew rate sections the next slices of

specialized designed components step on a 40

micron wide pattern. The first of these 40 micron

wide sections is utilized for predriver circuits; these

include specialized built in test functions for the I/O.

The predriver of course interfaces the core signals

controlling tristate and switching functions with the

slew rate and output transistor sections but it also

allows all Output Buffers to be driven high, low or

put into tristate regardless of the state of the internal

logic greatly simplifying parametric testing of the

part and also assisting customers who wish to use

this feature during board testing. Note that all output

ISB35000 SERIES

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