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L6611

18

3V3

3V3 UV/OV monitor. It uses a separate reference to the feedback reference.

19

5V

Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference

separate from that used for feedback. This pin connects the 5V part of the Main error amplifier

feedback divider.

20

12V

Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a

reference separate from that used for feedback. This pin connects the 12V part of the Main error

amplifier feedback divider.

FUNCTION DESCRIPTION

Name

Description

OVP

Whenever one of the Main output voltages is detected going above its own OVP threshold, this

function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON

(#13) switch or by reducing Vdd (#10) below the UV threshold.

UVP

Whenever one of the Main output voltages is detected going under its own UVP threshold, this

function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched.

Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#11) is

low due to a brownout condition, UVP is disabled.

UVB

Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits

must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the

auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts

as the ACsns pin detects a valid input voltage for the converter.

PW-OK delay

PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV

threshold the PW-OK pin (#12) will be kept low for additional 250ms (typ.) to make sure all the

outputs are settled.

OFF delay

Power-off delay. As soon as PS-ON (#13) pin is recognized high, indicating an imminent turn-off

condition, PW-OK (#12) pin will go low immediately . The converter will be turned off after a

delay of 2.5ms.

Debounce

The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored

inputs have digital filtering/debounce logic on board for high noise immunity.

AC-hysteresis

AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#11) to avoid

undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the

voltage ripple across the bulk capacitor.

Vdd-OVP

Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#9)

are latched high.

Vdd-UVL

To prevent false signals of any of IC’s output pins, an under voltage lock-out circuit monitors Vdd

and keeps all IC’s output at their default OFF level until Vdd reaches a sufficient minimum

voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and

volatile programming memory cleared.

Dual-OVP

Dmon (#8) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and

DFAULT (#9) are latched high.

Dual-UVP

Dmon (#8) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is latched

high and Cout (#6) is pulled low.

PIN DESCRIPTION (continued)

Pin #

Name

Description