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LM2653MTC-ADJ 데이터시트(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
부품명 LM2653MTC-ADJ
상세설명  1.5A High Efficiency Synchronous Switching Regulator
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2653MTC-ADJ 데이터시트(HTML) 9 Page - National Semiconductor (TI)

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Design Procedure (Continued)
R
1 and R2 (PROGRAMMING OUTPUT VOLTAGE)
Use the following formula to select the appropriate resistor
values:
V
OUT =VREF(1+R1/R2)
where V
REF = 1.238V
Select resistors between 10k
Ω and 100kΩ. (1% or higher
accuracy metal film resistors for R
1 and R2.)
COMPENSATION COMPONENTS
In the control to output transfer function, the first pole F
p1 can
be estimated as 1/(2
πR
OUTCOUT); The ESR zero Fz1 of the
output capacitor is 1/(2
πESRC
OUT); Also, there is a high
frequency pole F
p2 in the range of 45kHz to 150kHz:
F
p2 =Fs/(
πn(1−D))
whereD=V
OUT/VIN, n = 1+0.348L/(VIN−VOUT)(L isinµHs
and V
IN and VOUT in volts).
The total loop gain G is approximately 500/I
OUT where IOUT
is in amperes.
A Gm amplifier is used inside the LM2653. The output resis-
tor R
o of the Gm amplifier is about 80k
Ω.C
c1 and RC
together with R
o give a lag compensation to roll off the gain:
F
pc1 = 1/(2
πC
c1(Ro+Rc)), Fzc1 = 1/2
πC
c1Rc.
In some applications, the ESR zero F
z1 can not be cancelled
by F
p2. Then, Cc2 is needed to introduce Fpc2 to cancel the
ESR zero, F
p2 = 1/(2
πC
c2Ro\Rc).
The rule of thumb is to have more than 45˚ phase margin at
the crossover frequency (G=1).
If C
OUT is higher than 68µF, Cc1 = 2.2nF, and Rc = 15K
Ω are
good choices for most applications. If the ESR zero is too
low to be cancelled by F
p2, add Cc2.
If the transient response to a step load is important, choose
R
C to be higher than 10k
Ω.
EXTERNAL SCHOTTKY DIODE
A Schottky diode D
1 is recommended to prevent the intrinsic
body diode of the low-side MOSFET from conducting during
the deadtime in PWM operation and hysteretic mode when
both MOSFETs are off. If the body diode turns on, there is
extra power dissipation in the body diode because of the
reverse-recovery current and higher forward voltage; the
high-side MOSFET also has more switching loss since the
negative diode reverse-recovery current appears as the
high-side MOSFET turn-on current in addition to the load
current. These losses degrade the efficiency by 1-2%. The
improved efficiency and noise immunity with the Schottky
diode become more obvious with increasing input voltage
and load current.
The breakdown voltage rating of D
1 is preferred to be 25%
higher than the maximum input voltage. Since D
1 is only on
for a short period of time, the average current rating for D
1
only requires being higher than 30% of the maximum output
current. It is important to place D
1 very close to the drain and
source of the low-side MOSFET, extra parasitic inductance
in the parallel loop will slow the turn-on of D
1 and direct the
current through the body diode of the low-side MOSFET.
PCB Layout Considerations
Layout is critical to reduce noises and ensure specified
performance. The important guidelines are listed as follows:
1.
Minimize the parasitic inductance in the loop of input
capacitors and the internal MOSFETs by connecting the
input capacitors to V
IN and PGND pins with short and
wide traces. This is important because the rapidly
switching current, together with wiring inductance can
generate large voltage spikes that may result in noise
problems.
2.
Minimize the trace from the center of the output resistor
divider to the FB pin and keep it away from noise
sources to avoid noise pick up. For applications require
tight regulation at the output, a dedicated sense trace
(separated from the power trace) is recommended to
connect the top of the resistor divider to the output.
3.
If the Schottky diode D
1 is used, minimize the traces
connecting D
1 to SW and PGND pins.
10104901
Schematic for the Typical Board Layout
www.national.com
9


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