SL811S/T
Document #: 38-08009 Rev. **
Page 7 of 27
The SL811S/T write or read operation terminates when either nWR or nCS becomes inactive. For devices interfacing to the
SL811S/T that deactivate the Chip Select nCS before the write nWR, the data hold timing should be measured from the nCS and
will be the same value as specified. Thus, both Intel and Motorola type CPUs work well with SL811S/T without any external glue
logic required.
4.5
DMA Controller
In applications that require transfers of large amounts of data such as scanner interfaces, the SL811S/T provides a DMA interface.
This interface supports DMA read or write transfers to the SL811S/T internal RAM buffer through the microprocessor data bus
via two control lines: nDRQ (Data Request) and nDACK (Data Acknowledge), and along with the nWR line, controls the data flow
into the SL811S/T. The SL811S/T has a count register that allows programmable block sizes to be selected for DMA transfer. The
control signals interface—both nDRQ and nDACK—are designed to be compatible with standard DMA interfaces.
4.6
Interrupt Controller
The SL811S/T interrupt controller provides a single output signal. The INTR can be activated by a number of events that may
occur as a result of USB activity. Control and status registers are provided to allow you to select single or multiple events that will
generate an interrupt (assert INTR), and provide a means of viewing the interrupt status. The interrupt can be cleared by writing
to the Status Register located in the internal register space at address 0x0d.
4.7
Buffer Memory
The SL811S/T contains 256 bytes of internal buffer memory. The first 64 bytes of memory represent the control register, status
registers, and Endpoint registers for programmed I/O operations. The remaining memory locations are used for data buffering
(max 192 Bytes).
Access to the registers and data memory is done by an external microprocessor through the 8-bit data bus. This can be in either
of two addressing modes - indexed or direct access. With indexed addressing, the address is first written into the device with the
A0 address line Low, then the following cycle with A0 address line High is directed to the specified address. USB transactions
are automatically routed to the memory buffer. Control registers are provided to set up pointers and block sizes in buffer memory.
4.8
USB Transceiver
The SL811S/T has a built in transceiver that meets USB Specification 1.1. The transceiver is capable of transmitting and receiving
serial data at USB full speed (12 Mbits/sec) and slow speed (1.5 Mbits/sec). The driver portion of the transceiver is differential,
while the receiver section is comprised of a differential receiver and two single ended receivers. Internally, the transceiver
interfaces to the Serial Interface Engine, (SIE), logic. Externally the transceiver connects to the physical layer of the USB.
4.9
PLL Clock Generator
A 48-MHz external crystal can be used with the SL811S/T. Two pins, X1 and X2, are provided to connect a low cost crystal circuit
to the device (refer to Figure 4-1). If an external 48-MHz clock source is available in the application, it may be used instead of
the crystal circuit by connecting directly to the X1 input pin.
The SL811S/T contains a built-in DPLL and 4X Clock Multiplier, which can be enabled by setting a register bit and driving the CM
pin high, which allows operation with a 12 Mhz crystal or clock source. A suggested crystal circuit is shown in Figure 4-2.
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
