AD1934

Rev. 0 | Page 10 of 28

Pin No.

In/Out

Mnemonic

Description

26

I

CCLK/SCL

Control Clock Input (SPI).

27

I

CLATCH/ADR1

Latch Input for Control Data (SPI).

28

O

OL1

DAC 1 Left Output.

29

O

OR1

DAC 1 Right Output.

30

O

OL2

DAC 2 Left Output.

31

O

OR2

DAC 2 Right Output.

32

I

AGND

Analog Ground.

33

I

AVDD

Analog Power Supply. Connect to analog 3.3 V supply.

34

I

AGND

Analog Ground.

35

O

FILTR

Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.

36

I

AGND

Analog Ground.

37

I

AVDD

Analog Power Supply. Connect to analog 3.3 V supply.

38

O

CM

Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.

39 to 46

NC

Must Be Tied to Common Mode, Pin 38. Alternately, ac-coupled to ground.

47

O

LF

PLL Loop Filter. Return to AVDD.

48

I

AVDD

Analog Power Supply. Connect to analog 3.3 V supply.