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STK16CA8 데이터시트(PDF) 3 Page - Simtek Corporation |
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STK16CA8 데이터시트(HTML) 3 Page - Simtek Corporation |
3 / 12 page STK16CA8 September 2003 3 Document Control # ML0023 rev 0.1 SRAM READ CYCLES #1 & #2 (VCC = 3.0V +20%, -10%) Note f: W must be high during SRAM READ cycles. Note g: Device is continuously selected with E and G both low. Note h: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g SRAM READ CYCLE #2: E Controlledf NO. SYMBOLS PARAMETER STK16CA8-25 STK16CA8-35 STK16CA8-45 UNITS #1, #2 Alt. MINMAX MINMAX MINMAX 1tELQV tACS Chip Enable Access Time 25 35 45 ns 2tAVAVf tRC Read Cycle Time 25 35 45 ns 3tAVQVg tAA Address Access Time 25 35 45 ns 4tGLQV tOE Output Enable to Data Valid 10 15 20 ns 5tAXQXg tOH Output Hold after Address Change 3 3 3 ns 6tELQX tLZ Chip Enable to Output Active 3 3 3 ns 7tEHQZh tHZ Chip Disable to Output Inactive 10 13 15 ns 8tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9tGHQZh tOHZ Output Disable to Output Inactive 10 13 15 ns 10 tELICCHe tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICCLe tPS Chip Disable to Power Standby 25 35 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQX STANDBY DATA VALID 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 10 tELICCH 11 tEHICCL 7 tEHQZ 8 tGLQX 1 tELQV 9 tGHQZ |
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