2

Functional Diagram

TRUTH TABLE

INPUTS

OUTPUTS

RESET

(MR)

CLOCK

CP

DATA

Dn

Qn

LX

XL

H

↑

HH

H

↑

LL

HL

X

Q0

H = High level (steady state), L = Low level (steady state), X = Irrel-

evant,

↑ = Transition from Low to High level, Q0 = The level of Q

before the indicated steady-state input conditions were estab-

lished.

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

RESET MR

D0

D1

D2

D3

D4

D5

D6

D7

CLOCK

CP

DATA

INPUTS

DATA

OUTPUTS

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273