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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GS1561 데이터시트(PDF) 10 Page - Gennum Corporation |
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GS1561 데이터시트(HTML) 10 Page - Gennum Corporation |
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10 / 80 page  GS1560A/GS1561 Data Sheet 27360 - 10 January 2007 10 of 80 14 CD2 Non Synchronous Input STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI2 and DDI2 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid. In this case, the LOCKED signal is set LOW and all parallel outputs are muted. 15, 17 DDI2, DDI2 Analog Input Differential input pair for serial digital input 2. 16 TERM2 Analog Input Termination for serial digital input 2. AC couple to PDBUFF_GND. 18 SMPTE_BYPASS Non Synchronous Input / Output CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be an input set by the application layer in slave mode, and will be an output set by the device in master mode. Master Mode (MASTER/SLAVE = HIGH) The SMPTE_BYPASS signal will be HIGH only when the device has locked to a SMPTE compliant data stream. It will be LOW otherwise. Slave Mode (MASTER/SLAVE = LOW) When set HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When set LOW, the device will not support the descrambling, decoding or word alignment of received SMPTE data. No I/O processing features will be available. 19 RSET Analog Input GS1560A Used to set the serial digital loop-through output signal amplitude. Connect to CD_VDD through 281 Ω +/- 1% for 800mVp-p single-ended output swing. NC – – GS1561 No Connect. 20 CD_VDD – Power GS1560A Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog. NC – – GS1561 No Connect. 21 SDO_EN/DIS Non Synchronous Input GS1560A CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the serial digital output loop-through stage. When set LOW, the serial digital output signals SDO and SDO are disabled and become high impedance. When set HIGH, the serial digital output signals SDO and SDO are enabled. NC – – GS1561 No Connect. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
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