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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

30

35

40

45

Time − ns

Output

Input

Switching Characteristics

AUP

LVC

AUP

AUP

LVC

Static-Power Consumption

(

µA)

Dynamic-Power Consumption

(pF)

3.3-V

3.3-V

0%

20%

40%

60%

80%

100%

0%

20%

40%

60%

80%

100%

SN74AUP1G02

LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE

SCES568D – JUNE 2004 – REVISED MAY 2007

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

ORDERING INFORMATION

ORDERABLE PART NUMBER

NanoFree™ – WCSP (DSBGA)

Reel of 3000

SN74AUP1G02YFPR

PREVIEW

0.23-mm Large Bump – YFP (Pb-free)

NanoFree™ – WCSP (DSBGA)

Reel of 3000

SN74AUP1G02YZPR

PREVIEW

0.23-mm Large Bump – YZP (Pb-free)

–40

°C to 85°C SON – DRY

Reel of 5000

SN74AUP1G02DRYR

PREVIEW

SOT (SOT-23) – DBV

Reel of 3000

SN74AUP1G02DBVR

H02_

SOT (SC-70) – DCK

Reel of 3000

SN74AUP1G02DCKR

HB_

SOT (SOT-553) – DRL

Reel of 4000

SN74AUP1G02DRLR

HB_

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(3)

DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.

YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,

• = Pb-free).

FUNCTION TABLE

INPUTS

OUTPUT

Y

A

B

L

L

H

L

H

L

H

L

L

H

H

L

LOGIC DIAGRAM (POSITIVE LOGIC)

2

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