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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TSB12C01A 데이터시트(PDF) 6 Page - Texas Instruments |
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TSB12C01A 데이터시트(HTML) 6 Page - Texas Instruments |
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6 / 38 page  TSB21LV03 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SLLS230A – MARCH 1996 – REVISED DECEMBER 1996 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL TYPE I/O DESCRIPTION NAME NO. TYPE I/O DESCRIPTION AGND 26, 32, 41, 49, 50, 61 Supply — Analog circuit ground. All AGND terminals should be tied together to the low-impedance circuit-board ground plane. AVDD 24, 25, 51, 55 Supply — Analog circuit power. A combination of high frequency decoupling capacitors near each AVDD terminal is suggested, such as 0.1-µF and 0.001-µF capacitors. Lower frequency 10- µF filtering capacitors are also recommended. AVDD terminals are separated from DVDD terminals internally from the other supply terminals to provide noise isolation. They should be tied together at a low-impedance point on the circuit board. Each supply source should be individually filtered. C/LKON 27 CMOS I/O Bus manager capable (input). When set as an input, C/LKON specifies in the Self-ID packet that the node is bus manager capable. Link-on (output). When set as an output, C/LKON indicates the reception of a link-on mes- sage by asserting a 6.114-MHz signal. The bit value programming is done by tying the termi- nal through a 10-k Ω resistor to VDD (high, bus manager capable) or to GND (low, not bus manager capable). Using either the pullup or pulldown resistor allows the C/LKON output to override the input value when necessary. CNA 31 CMOS O Cable-not-active output. CNA is asserted high when none of the TSB21LV03 ports are con- nected to another active port. This circuit remains active during the power-down mode. CPS 23 CMOS I Cable power status. CPS is normally connected to the cable power through a 400-k Ω resis- tor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in two internal registers and is available to the LLC by way of a register read (see the Phy-Link Interface Annex in the IEEE 1394-1995 standard). CTL0 CTL1 11 12 CMOS I/O Control I/O. The CTLn terminals are bidirectional communications control signals between the TSB21LV03 and the LLC. These signals control the passage of information between the two devices. Control I/O terminals are 5-V tolerant. D0 – D3 13, 14, 15, 16 CMOS I/O Data I/O. The D terminals are bidirectional and pass data between the TSB21LV03 and the LLC. Data I/O terminals are 5-V tolerant. DGND 8, 10, 17, 18, 63, 64 Supply — Digital circuit ground. The DGND terminals should be tied to the low-impedance circuit-board ground plane. DVDD 5, 6, 19, 20 Supply — Digital circuit power. DVDD supplies power to the digital portion of the device. It is recom- mended that a combination of high-frequency decoupling capacitors be connected to DVDD (i.e., paralleled 0.1 µF and 0.001 µF). Lower frequency 10-µF filtering capacitors can also be used. These supply terminals are separated from AVDD internally in the device to provide noise isolation. These terminals should also be tied at a low-impedance point on the circuit board. Individual filtering networks for each is desired. FILTER 54 CMOS I/O PLL filter. FILTER is connected to a 0.1- µF capacitor and then to PLLGND to complete the internal lag-lead filter. This filter is required for stable operation of the frequency multiplier PLL running off of the crystal oscillator. ISO 62 CMOS I Link interface isolation disable input. ISO controls the operation of an internal pulse differen- tiating function used on the phy-LLC interface terminals, CTLn and Dn, when they operate as outputs. When ISO is asserted low, the optional isolation barrier is implemented between TSB21LV03 and its LLC (as described in Annex J of IEEE 1394-1995). ISO is normally tied high to disable isolation differentiation. LPS 2 CMOS I Link power status. LPS is connected to either the VDD supplying the LLC or to a pulsed out- put that is active when the LLC is powered for the purpose of monitoring the LLC power sta- tus. The pulsed signal must be between 220 kHz and 5.5 MHz to be sensed as active. If LPS is inactive, the phy-LLC interface is disabled, and the TSB21LV03 performs only the basic repeater functions required for network initialization and operation. LPS is 5-V tolerant. LREQ 3 CMOS I Link request. LREQ is an input from the LLC that requests the TSB21LV03 to perform some service. LREQ is 5-V tolerant. PC0 – PC2 28, 29, 30 CMOS I Power class indicators. The PC signals set the bit values of the three power-class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be programmed by tying the terminals to VDD (high) or to GND (low). PD 7 CMOS I Power down. When asserted high, PD turns off all internal circuitry except the CNA monitor circuits that drive the CNA terminal. PD is 5-V tolerant. |
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