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CAT1161LI-28-GT3 데이터시트(PDF) 7 Page - Catalyst Semiconductor |
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CAT1161LI-28-GT3 데이터시트(HTML) 7 Page - Catalyst Semiconductor |
7 / 14 page CAT1161, CAT1162 © Catalyst Semiconductor, Inc. 7 Doc. No. MD-3002 Rev. G Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT1161/2 supports the I 2C Bus data transmis– sion protocol. This Inter-Integrated Circuit Bus proto– col defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I 2C BUS PROTOCOL The features of the I 2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1161/2 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010. The next three bits (Figure 6) define memory addressing. For the CAT1161/2 the three bits define higher order bits. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT1161/2 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1161/2 then performs a Read or Write operation depending on the R/W ¯¯ bit. Figure 5. Acknowledge Timing Figure 6. Slave Address Bits CAT1161/2 1 0 1 0 a10 a9 a8 R/W ¯¯ **a8, a9 and a10 correspond to the address of the memory array address word. ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER |
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