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SN74ABT18504PMR 데이터시트(PDF) 7 Page - Texas Instruments |
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SN74ABT18504PMR 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 34 page SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS108B – AUGUST 1992 – REVISED JUNE 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 state diagram description The test access port (TAP) controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As illustrated, the TAP controller consists of sixteen states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths though the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers may also be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the ′ABT18504, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Each bit in the boundary-scan register is reset to logic 0 except bits 87 – 86, which are reset to logic 1. The boundary-control register is reset to the binary value 00000000000000000000010, which selects the PSA test operation with no input masking. Run-Test/Idle The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state can also be entered following data register or instruction register scans. Run-Test/Idle is provided as a stable state in which the test logic may be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states are provided to allow the selection of either data register scan or instruction register scan. Capture-DR When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR state. |
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