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74ALVCH16821DLRG4 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Texas Instruments

๋ถ€ํ’ˆ๋ช… 74ALVCH16821DLRG4
์ƒ์„ธ๋‚ด์šฉ  3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
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74ALVCH16821DLRG4 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Texas Instruments

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PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + Vโˆ†
VOH โˆ’ Vโˆ†
0 V
VI
0 V
0 V
tw
VI
VI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
โ‰ค 10 MHz, ZO = 50 โ„ฆ.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VM
VM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
VM
tPLH
VLOAD
VLOAD/2
1.8 V
2.5 V
ยฑ 0.2 V
2.7 V
3.3 V
ยฑ 0.3 V
1 k
โ„ฆ
500
โ„ฆ
500
โ„ฆ
500
โ„ฆ
VCC
RL
2
ร— VCC
2
ร— VCC
6 V
6 V
VLOAD
CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
Vโˆ†
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
โ‰ค2 ns
โ‰ค2 ns
โ‰ค2.5 ns
โ‰ค2.5 ns
INPUT
SN74ALVCH16821
3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES037F โ€“ JULY 1995 โ€“ REVISED SEPTEMBER 2004
Figure 1. Load Circuit and Voltage Waveforms
6


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