2

Feb, 2008

Document Control #ML0014 Rev 2.0

STK14C88

PIN CONFIGURATIONS

PIN DESCRIPTIONS

Pin Name

I/O

Description

Input

Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM

E

Input

Chip Enable: The active low E input selects the device

W

Input

Write Enable: The active low W enables data on the DQ pins to be written to the address

location latched by the falling edge of E

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

Power Supply

Power: 5.0V, +10%

HSB

I/O

Hardware Store Busy: When low this output indicates a Store is in progress. When pulled

low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor

keeps this pin high if not connected. (Connection Optional).

Power Supply

AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from

SRAM to nonvolatile storage elements.

Power Supply

Ground

NC

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

E

NC

32

31

30

29

HSB

W

G

(TOP)

NC

NC

E

G

(TOP)

32-Pin 300 mil SOIC

32-Pin 300 mil CDIP

32-Pin 450 mil LCC