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LM3S8730-IQC20-A1T 데이터시트(PDF) 58 Page - List of Unclassifed Manufacturers

부품명 LM3S8730-IQC20-A1T
상세설명  Microcontroller
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The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
6.1.4.2
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
page 70 on page ? describes the available crystal choices and default programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.3
PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 74). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
page 70 on page ? describes the available crystal choices and default programming of the PLLCFG
register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration
(RCC) register. Any time the XTAL field changes, the new settings are translated and the internal
PLL settings are updated.
6.1.4.4
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 70 and page 75).
6.1.4.5
PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
20-5 on page 468). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
September 02, 2007
58
Preliminary
System Control


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