Description
Reset
Type
Name
Bit/Field
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Frequency (BYPASS=0)
Divisor (BYPASS=1)
Value
reserved
reserved
0x0
reserved
/2
0x1
reserved
/3
0x2
50 MHz
/4
0x3
40 MHz
/5
0x4
33.33 MHz
/6
0x5
28.57 MHz
/7
0x6
25 MHz
/8
0x7
22.22 MHz
/9
0x8
20 MHz
/10
0x9
18.18 MHz
/11
0xA
16.67 MHz
/12
0xB
15.38 MHz
/13
0xC
14.29 MHz
/14
0xD
13.33 MHz
/15
0xE
12.5 MHz (default)
/16
0xF
When reading the Run-Mode Clock Configuration (RCC) register (see
page 70), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
0xF
R/W
SYSDIV
26:23
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
0
R/W
USESYSDIV
22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
21:14
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1
R/W
PWRDN
13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RO
reserved
12
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
1
R/W
BYPASS
11
71
September 02, 2007
Preliminary
LM3S8730 Microcontroller