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LM3S8730-IQN20-A2T 데이터시트(PDF) 4 Page - List of Unclassifed Manufacturers

부품명 LM3S8730-IQN20-A2T
상세설명  Microcontroller
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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LM3S8730-IQN20-A2T 데이터시트(HTML) 4 Page - List of Unclassifed Manufacturers

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6.1.4
Clock Control ............................................................................................................................ 57
6.1.5
System Control ......................................................................................................................... 59
6.2
Initialization and Configuration ................................................................................................... 60
6.3
Register Map ............................................................................................................................ 60
6.4
Register Descriptions ................................................................................................................ 61
7
Hibernation Module .......................................................................................................... 111
7.1
Block Diagram ........................................................................................................................ 112
7.2
Functional Description ............................................................................................................. 112
7.2.1
Register Access Timing ........................................................................................................... 112
7.2.2
Clock Source .......................................................................................................................... 113
7.2.3
Battery Management ............................................................................................................... 113
7.2.4
Real-Time Clock ...................................................................................................................... 113
7.2.5
Non-Volatile Memory ............................................................................................................... 114
7.2.6
Power Control ......................................................................................................................... 114
7.2.7
Interrupts and Status ............................................................................................................... 114
7.3
Initialization and Configuration ................................................................................................. 115
7.3.1
Initialization ............................................................................................................................. 115
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 115
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 115
7.3.4
External Wake-Up from Hibernation .......................................................................................... 116
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 116
7.4
Register Map .......................................................................................................................... 116
7.5
Register Descriptions .............................................................................................................. 117
8
Internal Memory ............................................................................................................... 130
8.1
Block Diagram ........................................................................................................................ 130
8.2
Functional Description ............................................................................................................. 130
8.2.1
SRAM Memory ........................................................................................................................ 130
8.2.2
Flash Memory ......................................................................................................................... 131
8.3
Flash Memory Initialization and Configuration ........................................................................... 132
8.3.1
Flash Programming ................................................................................................................. 132
8.3.2
Nonvolatile Register Programming ........................................................................................... 133
8.4
Register Map .......................................................................................................................... 133
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 134
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 141
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 154
9.1
Functional Description ............................................................................................................. 154
9.1.1
Data Control ........................................................................................................................... 154
9.1.2
Interrupt Control ...................................................................................................................... 155
9.1.3
Mode Control .......................................................................................................................... 156
9.1.4
Commit Control ....................................................................................................................... 156
9.1.5
Pad Control ............................................................................................................................. 156
9.1.6
Identification ........................................................................................................................... 156
9.2
Initialization and Configuration ................................................................................................. 156
9.3
Register Map .......................................................................................................................... 157
9.4
Register Descriptions .............................................................................................................. 159
10
General-Purpose Timers ................................................................................................. 194
10.1
Block Diagram ........................................................................................................................ 195
September 02, 2007
4
Preliminary
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