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Description
End
Start
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
Instrumentation Trace Macrocell (ITM)
0xE000.0FFF
0xE000.0000
Data Watchpoint and Trace (DWT)
0xE000.1FFF
0xE000.1000
Flash Patch and Breakpoint (FPB)
0xE000.2FFF
0xE000.2000
Reserved
0xE000.DFFF
0xE000.3000
Nested Vectored Interrupt Controller (NVIC)
0xE000.EFFF
0xE000.E000
Reserved
0xE003.FFFF
0xE000.F000
Trace Port Interface Unit (TPIU)
0xE004.0FFF
0xE004.0000
-
Reserved
0xE004.1FFF
0xE004.1000
-
Reserved
0xE00F.FFFF
0xE004.2000
-
Reserved for vendor peripherals
0xFFFF.FFFF
0xE010.0000
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
September 02, 2007
40
Preliminary
Memory Map
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