LM3S317 Data Sheet
May 4, 2007
85
Preliminary
19:17
PWMDIV
R/W
0x7
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the
system clock down for use as the timing reference for the
PWM module. This clock is only power 2 divide and rising
edge is synchronous without phase shift from the system
clock.
16:14
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
13
PWRDN
R/W
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. See Table 6-4 on page 87 for
PLL mode control.
12
OEN
R/W
1
PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwise, the PLL clock does not oscillate outside the PLL
module.
Note:
Both PWRDN and OEN must be cleared to run the
PLL.
11
BYPASS
R/W
1
PLL Bypass
Chooses whether the system clock is derived from the PLL
output or the OSC source. If set, the clock that drives the
system is the OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Note:
The ADC module must be clocked from the PLL or
directly from a 14-MHz to an 18-MHz clock source
in order to operate properly.
Bit/Field
Name
Type
Reset
Description
Value
Divisor
000
/2
001
/4
010
/8
011
/16
100
/32
101
/64
110
/64
111
/64 (default)
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