List of Tables
Table 1.
Documentation Conventions ............................................................................................ 18
Table 3-1.
Memory Map ................................................................................................................... 40
Table 4-1.
Exception Types .............................................................................................................. 42
Table 4-2.
Interrupts ........................................................................................................................ 43
Table 5-1.
JTAG Port Pins Reset State ............................................................................................. 46
Table 5-2.
JTAG Instruction Register Commands ............................................................................... 51
Table 6-1.
System Control Register Map ........................................................................................... 61
Table 7-1.
Hibernation Module Register Map ................................................................................... 118
Table 8-1.
Flash Protection Policy Combinations ............................................................................. 134
Table 8-2.
Flash Resident Registers ............................................................................................... 135
Table 8-3.
Flash Register Map ........................................................................................................ 135
Table 9-1.
GPIO Pad Configuration Examples ................................................................................. 160
Table 9-2.
GPIO Interrupt Configuration Example ............................................................................ 160
Table 9-3.
GPIO Register Map ....................................................................................................... 161
Table 10-1.
Available CCP Pins ........................................................................................................ 198
Table 10-2.
16-Bit Timer With Prescaler Configurations ..................................................................... 201
Table 10-3.
Timers Register Map ...................................................................................................... 207
Table 11-1.
Watchdog Timer Register Map ........................................................................................ 234
Table 12-1.
Samples and FIFO Depth of Sequencers ........................................................................ 257
Table 12-2.
ADC Register Map ......................................................................................................... 260
Table 13-1.
UART Register Map ....................................................................................................... 294
Table 14-1.
SSI Register Map .......................................................................................................... 339
Table 15-1.
Examples of I2C Master Timer Period versus Speed Mode ............................................... 369
Table 15-2.
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 378
Table 15-3.
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 383
Table 16-1.
TX & RX FIFO Organization ........................................................................................... 405
Table 16-2.
Ethernet Register Map ................................................................................................... 408
Table 17-1.
PWM Register Map ........................................................................................................ 450
Table 19-1.
Signals by Pin Number ................................................................................................... 481
Table 19-2.
Signals by Signal Name ................................................................................................. 485
Table 19-3.
Signals by Function, Except for GPIO ............................................................................. 489
Table 19-4.
GPIO Pins and Alternate Functions ................................................................................. 492
Table 20-1.
Temperature Characteristics ........................................................................................... 494
Table 20-2.
Thermal Characteristics ................................................................................................. 494
Table 21-1.
Maximum Ratings .......................................................................................................... 495
Table 21-2.
Recommended DC Operating Conditions ........................................................................ 495
Table 21-3.
LDO Regulator Characteristics ....................................................................................... 496
Table 21-4.
Detailed Power Specifications ........................................................................................ 497
Table 21-5.
Flash Memory Characteristics ........................................................................................ 498
Table 21-6.
Phase Locked Loop (PLL) Characteristics ....................................................................... 498
Table 21-7.
Clock Characteristics ..................................................................................................... 498
Table 21-8.
Crystal Characteristics ................................................................................................... 499
Table 21-9.
ADC Characteristics ....................................................................................................... 499
Table 21-10.
I2C Characteristics ......................................................................................................... 500
Table 21-11.
100BASE-TX Transmitter Characteristics ........................................................................ 500
Table 21-12.
100BASE-TX Transmitter Characteristics (informative) ..................................................... 501
November 30, 2007
10
Preliminary
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