6.1.3
Power Control ........................................................................................................................... 58
6.1.4
Clock Control ............................................................................................................................ 58
6.1.5
System Control ......................................................................................................................... 60
6.2
Initialization and Configuration ................................................................................................... 61
6.3
Register Map ............................................................................................................................ 61
6.4
Register Descriptions ................................................................................................................ 62
7
Hibernation Module .......................................................................................................... 116
7.1
Block Diagram ........................................................................................................................ 117
7.2
Functional Description ............................................................................................................. 117
7.2.1
Register Access Timing ........................................................................................................... 117
7.2.2
Clock Source .......................................................................................................................... 118
7.2.3
Battery Management ............................................................................................................... 118
7.2.4
Real-Time Clock ...................................................................................................................... 118
7.2.5
Non-Volatile Memory ............................................................................................................... 119
7.2.6
Power Control ......................................................................................................................... 119
7.2.7
Interrupts and Status ............................................................................................................... 119
7.3
Initialization and Configuration ................................................................................................. 120
7.3.1
Initialization ............................................................................................................................. 120
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 120
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 120
7.3.4
External Wake-Up from Hibernation .......................................................................................... 121
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 121
7.4
Register Map .......................................................................................................................... 121
7.5
Register Descriptions .............................................................................................................. 122
8
Internal Memory ............................................................................................................... 135
8.1
Block Diagram ........................................................................................................................ 135
8.2
Functional Description ............................................................................................................. 135
8.2.1
SRAM Memory ........................................................................................................................ 135
8.2.2
Flash Memory ......................................................................................................................... 136
8.3
Flash Memory Initialization and Configuration ........................................................................... 137
8.3.1
Flash Programming ................................................................................................................. 137
8.3.2
Nonvolatile Register Programming ........................................................................................... 138
8.4
Register Map .......................................................................................................................... 138
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 139
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 146
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 159
9.1
Functional Description ............................................................................................................. 159
9.1.1
Data Control ........................................................................................................................... 159
9.1.2
Interrupt Control ...................................................................................................................... 160
9.1.3
Mode Control .......................................................................................................................... 161
9.1.4
Commit Control ....................................................................................................................... 161
9.1.5
Pad Control ............................................................................................................................. 161
9.1.6
Identification ........................................................................................................................... 162
9.2
Initialization and Configuration ................................................................................................. 162
9.3
Register Map .......................................................................................................................... 163
9.4
Register Descriptions .............................................................................................................. 165
October 08, 2007
4
Preliminary
Table of Contents