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3
Memory Map
The memory map for the LM3S8730 controller is provided in Table 3-1 on page 39.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 39, addresses not listed are reserved.
Table 3-1. Memory Map
a
For details on
registers, see
page ...
Description
End
Start
Memory
134
On-chip flash
b
0x0001.FFFF
0x0000.0000
134
Bit-banded on-chip SRAM
c
0x2000.FFFF
0x2000.0000
-
Reserved non-bit-banded SRAM space
0x21FF.FFFF
0x2010.0000
130
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
0x23FF.FFFF
0x2200.0000
-
Reserved non-bit-banded SRAM space
0x3FFF.FFFF
0x2400.0000
FiRM Peripherals
232
Watchdog timer
0x4000.0FFF
0x4000.0000
159
GPIO Port A
0x4000.4FFF
0x4000.4000
159
GPIO Port B
0x4000.5FFF
0x4000.5000
159
GPIO Port C
0x4000.6FFF
0x4000.6000
159
GPIO Port D
0x4000.7FFF
0x4000.7000
305
SSI0
0x4000.8FFF
0x4000.8000
260
UART0
0x4000.CFFF
0x4000.C000
260
UART1
0x4000.DFFF
0x4000.D000
Peripherals
344
I2C Master 0
0x4002.07FF
0x4002.0000
357
I2C Slave 0
0x4002.0FFF
0x4002.0800
159
GPIO Port E
0x4002.4FFF
0x4002.4000
159
GPIO Port F
0x4002.5FFF
0x4002.5000
159
GPIO Port G
0x4002.6FFF
0x4002.6000
205
Timer0
0x4003.0FFF
0x4003.0000
205
Timer1
0x4003.1FFF
0x4003.1000
205
Timer2
0x4003.2FFF
0x4003.2000
205
Timer3
0x4003.3FFF
0x4003.3000
379
CAN0 Controller
0x4004.0FFF
0x4004.0000
415
Ethernet Controller
0x4004.8FFF
0x4004.8000
117
Hibernation Module
0x400F.CFFF
0x400F.C000
134
Flash control
0x400F.DFFF
0x400F.D000
61
System control
0x400F.EFFF
0x400F.E000
-
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
0x43FF.FFFF
0x4200.0000
39
September 02, 2007
Preliminary
LM3S8730 Microcontroller