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LM3S8730-IQC50-A1 데이터시트(PDF) 22 Page - List of Unclassifed Manufacturers

부품명 LM3S8730-IQC50-A1
상세설명  Microcontroller
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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LM3S8730-IQC50-A1 데이터시트(HTML) 22 Page - List of Unclassifed Manufacturers

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Input edge count capture
Input edge time capture
16-bit PWM mode
Simple PWM mode with software-programmable output inversion of the PWM signal
ARM FiRM-compliant Watchdog Timer
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
Controller Area Network (CAN)
Supports CAN protocol version 2.0 part A/B
Bit rates up to 1Mb/s
32 message objects, each with its own identifier mask
Maskable interrupt
Disable automatic retransmission mode for TTCAN
Programmable loop-back mode for self-test operation
10/100 Ethernet Controller
Conforms to the IEEE 802.3-2002 Specification
IEEE 1588-2002 Precision Time Protocol (PTP) compliant
Full- and half-duplex for both 100 Mbps and 10 Mbps operation
Integrated 10/100 Mbps Transceiver (PHY)
Automatic MDI/MDI-X cross-over correction
Programmable MAC address
Power-saving and power-down modes
Synchronous Serial Interface (SSI)
Master or slave operation
Programmable clock bit rate and prescale
September 02, 2007
22
Preliminary
Architectural Overview


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