code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1.
Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2.
Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3.
Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV
field determines the system frequency for the microcontroller.
4.
Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5.
Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3
Register Map
Table 6-1 on page 60 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
page
Description
Reset
Type
Name
Offset
62
Device Identification 0
-
RO
DID0
0x000
78
Device Identification 1
-
RO
DID1
0x004
80
Device Capabilities 0
0x00FF.003F
RO
DC0
0x008
81
Device Capabilities 1
0x0100.30DF
RO
DC1
0x010
83
Device Capabilities 2
0x000F.1013
RO
DC2
0x014
85
Device Capabilities 3
0x0300.0000
RO
DC3
0x018
86
Device Capabilities 4
0x5100.007F
RO
DC4
0x01C
64
Brown-Out Reset Control
0x0000.7FFD
R/W
PBORCTL
0x030
65
LDO Power Control
0x0000.0000
R/W
LDOPCTL
0x034
106
Software Reset Control 0
0x00000000
R/W
SRCR0
0x040
September 02, 2007
60
Preliminary
System Control