Register 3:
Flash Memory Control (FMC), offset 0x008 ..................................................................... 137
Register 4:
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 139
Register 5:
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 140
Register 6:
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 141
Register 7:
USec Reload (USECRL), offset 0x140 ............................................................................ 142
Register 8:
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 143
Register 9:
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 144
Register 10:
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 145
Register 11:
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 146
Register 12:
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 147
Register 13:
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 148
Register 14:
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 149
Register 15:
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 150
Register 16:
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 151
Register 17:
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 152
Register 18:
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 153
General-Purpose Input/Outputs (GPIOs) ................................................................................... 154
Register 1:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 160
Register 2:
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 161
Register 3:
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 162
Register 4:
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 163
Register 5:
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 164
Register 6:
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 165
Register 7:
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 166
Register 8:
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 167
Register 9:
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 168
Register 10:
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 169
Register 11:
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 171
Register 12:
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 172
Register 13:
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 173
Register 14:
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 174
Register 15:
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 175
Register 16:
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 176
Register 17:
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 177
Register 18:
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 178
Register 19:
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 179
Register 20:
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 180
Register 21:
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 182
Register 22:
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 183
Register 23:
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 184
Register 24:
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 185
Register 25:
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 186
Register 26:
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 187
Register 27:
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 188
Register 28:
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 189
Register 29:
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 190
Register 30:
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 191
Register 31:
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 192
13
September 02, 2007
Preliminary
LM3S8730 Microcontroller
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